The present invention claims the benefit of Korean Patent Application No. P2000-76014 filed in Korea on Dec. 13, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a circuit for controlling a wordline in an SRAM, in which an enabled wordline is disabled after a preset time period of delay for reducing a current consumed at a cell in reading/writing the cell.
2. Discussion of the Related Art
Referring to FIG. 1, a related art SRAM device is provided with an X address decoder 10 for receiving, and decoding a series of X addresses, and selecting, and forwarding X addresses XD0, and XDI of a cell, a wordline driver 11 for receiving the selected X addresses XD0, and XDI, and providing a wordline enable signal WL of the cell, a cell block 12 having a plurality of wordlines respectively connected to a plurality of cells for storage of data, and bitlines formed perpendicular to the wordlines, a column collector 13 for selecting one of the bitlines BL, and {overscore (BL)} in the cell block, and a sense amplifier and a write driver 14 for amplifying, and forwarding a signal on a common dataline DL, and {overscore (DL)} of the column selector 13 by means of a sense amplifier in reading, and dividing a received data Din, and providing the divided data to the common datalines DL, and {overscore (DL)} respectively by means of a write driver. The sense amplifier is driven in response to a sense amplifier enable signal SEN, and the write driver is driven in response to a write driver enable signal WDEN.
The operation of the related art SRAM will be explained with reference to FIGS. 2A-2B.
In writing, the X address decoder receives, and decodes the X addresses, and forwards XD0 and XDI. For representing a write pad input waveform being a write, {overscore (WE)} is transited to a low state. The wordline driver 11 is actuated in response to the XD0 and XDI signals, to provide a high level wordline enable signal WL. When the high level wordline enable signal WL is provided to the cell block 12, a preset selected wordline in the cell block 12, i.e., ROW cells are enable to an actuated state.
In the meantime, when {overscore (WE)} is transited to a low state, making the write driver enable signal WDEN kept at a low state, the write driver in the sense amplifier and write driver 14 is enabled, to produce a low, or high level potential difference between the common datalines DL, and {overscore (DL)} when a data DIN to be written on a preset cell in the cell block is received. Then, the column selector 13 selects one of the bitlines BL, and {overscore (BL)} according to the potential difference, to select a cell of an enabled wordline to write the data thereon.
Referring to FIG. 2B, in reading, the word driver 11 receives the XD0, and XDI decoded and provided from the X addresses, and enables a wordline. The enabled wordline selects a cell in the cell block 12, to discharge one of the bitline BL, and the bitline {overscore (BL)} having an inverted potential of the bitline BL, both of which are connected to the wordline, so that the column selector 13 provides the potential of the pair of the bitlines to the common dataline. As the potential difference is sensed, and amplified by the sense amplifier (in this instance, since it is a reading mode, {overscore (WE)} is at a high level, and the SEN is at a high level, which is a enable state), a data output signal DOUT is read.
However, currents flow to the selected row cells of the related art SRAM in response to the wordline enable signal in writing or reading, and, if there is no change of a state of the wordline enable signal caused by the next writing or reading, the wordline maintains the enabled state, to make the current to flow to the cell, always.
That is, as can be known from FIGS. 2A-2B, because the related art SRAM has a great power consumption caused by continuous flow of cell current until selection of the next wordline coming from the wordline enable signal WL kept at a high state even after the wordline, i.e., a row cell, is enabled in response to the wordline enable signal WL, and reads, or writes a data, which power consumption is the greater as the operative voltage is the higher, the related art SRAM is not suitable to recent SRAM devices which require a low power consumption.
Accordingly, the present invention is directed to a circuit for controlling a wordline in an SRAM that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for controlling a wordline in an SRAM, in which a wordline enable signal at an enabled state even after data reading or writing is disabled, for preventing a power consumption of the cell.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a circuit for controlling a wordline in an SRAM includes an X address decoder for receiving and decoding a series of X addresses, and forwarding X addresses of a relevant cell, a cell block having a plurality of wordlines respectively connected to cells for storage of data, and a plurality of bitlines perpendicular to the wordlines, a wordline driver for receiving the X addresses, and forwarding a wordline enable signal for the cell block, a column selector for selecting one pair of bitlines from the plurality of bitlines, a sense amplifier for amplifying, and forwarding an output of the column selector in reading, a write driver for receiving, and providing a driving signal, and a wordline control part for selecting one of a write driver enable signal in writing and a sense amplifier enable signal in reading in response to a read/write identifying signal, to generate a control signal, and forward the control signal after delay of a preset time period, for disabling the wordline.
In another aspect, a method for controlling a wordline in an SRAM includes receiving and decoding a series of X addresses via an X address decoder, forwarding X addresses of a relevant cell, storing data via a cell block having a plurality of wordlines respectively connected to cells, receiving the X addresses via a wordline driver, forwarding a wordline enable signal for the cell block, selecting one pair of bitlines from the plurality of bitlines via a column selector, amplifying, and forwarding an output of the column selector in reading via a sense amplifier, receiving, and providing a driving signal via a write driver, and selecting one of a write driver enable signal in writing and a sense amplifier enable signal in reading in response to a read/write identifying signal, to generate a control signal, and forward the control signal after delay of a preset time period, for disabling the wordline via a wordline control part.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.